The present invention relates to a circuit for generating an operation voltage of a non-volatile memory device. More particularly, the present invention relates to a circuit for generating a voltage in accordance with program state of a memory cell and an ambient temperature, and a non-volatile memory device having the same.
A semiconductor memory device is a memory device for storing data and reading the data when appropriate. This semiconductor memory device includes a volatile memory in which data are erased when power is turned off and a non-volatile memory in which data are not erased even though power is turned off.
A flash memory erases electrically and collectively data in a memory cell, and so the flash memory is widely used in computers and memory cards, etc.
A memory cell in the non-volatile memory device has a current path formed between a source and a drain on a semiconductor substrate, and a floating gate and a control gate located between insulating layers on the semiconductor substrate.
A program operation of the flash memory cell is generally performed through Fowler-Nordheim tunneling (hereinafter, referred to as “F-N tunneling”) generated by applying a high program voltage Vpp having a positive level, e.g. 15V to 20V, to the control gate after connecting source/drain areas and the semiconductor substrate, i.e. bulk area to a ground. Here, an electric field, generated by the voltage Vpp applied to the control gate, moves electrons of the bulk area to the floating gate through F-N tunneling, thereby increasing a threshold voltage of the memory cell.
An erase operation of the memory cell is performed through F-N tunneling generated by applying a high erase voltage Vera having a negative level, e.g. −10V to the control gate and applying a certain voltage, e.g. −5V to the bulk area, and is simultaneously performed in a unit of a sector sharing the bulk area.
The F-N tunneling outputs the electrons in the floating gate to the source area, and thus the memory cells have erase threshold voltage distributions of about −2V to −3V.
It has been determined that a memory cell, in which a threshold voltage is increased in accordance with the program operation, is turned off because current is not injected from the drain area to the source area in a read operation. However, it has also been determined that a memory cell, in which a threshold voltage is reduced in accordance with the erase operation, is turned on because current is injected from the drain area to the source area.
As mentioned above, the non-volatile memory device performs the read operation for reading data and a verifying operation by applying a fixed read voltage and a verifying voltage to a gate of a selected memory cell. Here, the threshold voltage distribution of the memory cell may be changed in accordance with temperature, and so a read margin may be reduced. As a result, undesired data may be read.
FIG. 1A is a view illustrating threshold voltage distributions of memory cells in a non-volatile memory device.
In FIG. 1A, a memory cell for storing two bit information in a non-volatile memory device, has four threshold voltage distributions. In this case, a threshold voltage of the memory cell is changed in accordance with an ambient temperature as shown in FIG. 1A. Here, the higher the threshold voltage of the memory cell is, the smaller the change in the threshold voltage.
FIG. 1B is a view illustrating change of a threshold voltage of a memory cell in accordance with temperature.
FIG. 1B shows threshold voltage distributions of memory cells programmed at high temperature H (CASE1), normal temperature R (CASE2) and low temperature C (CASE3), threshold voltage distributions 151 of erased memory cells in a read operation, and threshold voltage distributions 152 of programmed memory cells.
As shown in FIG. 1B, in a case where the verifying voltage is fixed, the threshold voltage of the memory cell is increased accordingly as the temperature is augmented when the program operation is performed. However, in a case where data of the memory cell is read after the program operation is performed, the threshold voltage of the memory cell is reduced accordingly as the temperature is increased.
That is, in CASE1, the difference between the read voltage and the threshold voltage of a programmed memory cell ‘0’ in the read operation is minimized when the program operation is performed at low temperature and the read operation is performed at high temperature. Accordingly, in the case of reading the memory cell ‘0’, data of the memory cell may be misread as ‘1’ instead of ‘0’.
In CASE 3, the difference between the read voltage and the threshold voltage of a programmed memory cell ‘1’ in the read operation is minimized when the program operation is performed at high temperature and the read operation is performed at low temperature. Accordingly, data of the memory cell may be misread as ‘0’ instead of ‘1’.
FIG. 2A is a block diagram illustrating a read voltage generator that is not affected by a temperature, and FIG. 2B is a view illustrating a graph showing the relation between output voltage and temperature.
In FIG. 2A and FIG. 2B, the read voltage generator 200 for outputting a read voltage Vread for a read operation adjusts the level of the read voltage Vread in accordance with a bias option bit, and outputs the adjusted read voltage Vread.
As shown in FIG. 2B, the read voltage Vread outputted from the read voltage generator 200 is reduced accordingly as the temperature is increased.
As described above, the possibility of a read error of the data is increased or reduced in accordance with the difference between the temperature for the program operation and the temperature for the read operation.